1. Field of the Invention
The present invention relates to integrated circuit devices, cell libraries, cell architectures and electronic design automation tools for integrated circuit devices.
2. Description of Related Art
In the design of integrated circuits, standard cell libraries are often utilized. The process of designing the cells specified by entries in the cell libraries can be intensive, where trade-offs among variables such as the size of the cells, the drive power of the cells, the speed of the cells and so on, are made by adjusting the materials, geometry and size of the components of the cell. The procedure of designing cells to be specified in a cell library is often a labor-intensive process, requiring highly skilled designers to manually design and refine the designs of the cells.
The development of finFETs has provided some additional flexibility for designers which can be applied in the efficient design of variations of specific cells. Thus, some functional libraries are based on finFETs. FinFETs have been implemented in block structures having a grid structure, in which fins are laid out in parallel in a first direction on a substrate with a narrow pitch, and gates are laid out in an orthogonal direction across the fins. The individual cells are formed using sets of complementary re-channel and p-channel transistors having their source, drain and channel in the fins. The drive power and other characteristics of individual transistors in a cell utilizing finFETs can be adjusted by increasing or decreasing the number of identical fins utilized in parallel as the channel structure for a given transistor. This provides some granularity of design in the development of a cell library. However, many circuit parameters can benefit from finer tuning of circuit structures. To fine tune finFET type circuits, complex reconfiguration of the fins or other structures may be required.
The following documents describe developments in the nanowire and 2D material field, and are incorporated by reference for all information presented therein:                Van der Waals Heterostructures, A. K. Geim et al., 25 Jul. 2013|VOL 499|NATURE|419-425;        Vertically Integrated Nanowire Field Effect Transistors, Josh Goldberger et al., Department of Chemistry, University of California, Berkeley, and Materials Science Division, Lawrence Berkeley National Laboratory;        Silicon Vertically Integrated Nanowire Field Effect Transistors, Josh Goldberger et al., Nano Letters, 2006 Vol. 6, No. 5 973-977;        Controlled Growth of Si Nanowire Arrays for Device Integration, Allon I. Hochbaum et al., Nano Letters, 2005 Vol. 5, No. 3 457-460;        Modeling of Stress-retarded Orientation-dependent Oxidation: Shape Engineering of Silicon Nanowire Channels, F.-J ma et al., 97-4244-5640-6/09 ©2009 IEEE, IEDM09-517-520, 21.5.1-21.5.4;        Energy Efficiency Comparison of Nanowire Heterojunction TFET and Si MOSFET at Lg=13 nm, Including P-TFET and Variation Considerations, Uygar E. Avci et al., 978-1-4799-2306-9/13 ©2013 IEEE, IEDM13-830-833, 33.4.1-33.3.4;        US Patent Application Publication No. 2014/0015135, Pub. Date Jan. 16, 2014, titled Self-Aligned Via Interconnect Using Relaxed Patterning Exposure, Michael L. Rieger et al.;        Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with Metal/High-K Gate stack, E. Bernard et al., 978-1-4244-1805-3/08 © 2008, 16-17.        
It is desirable to provide a cell design architecture suitable for implementation of cells for a cell library that can provide for finer variations in circuit parameters while reducing the design time and design effort required.